## 职缺一览 ##
Senior Compiler/Virtual Machine Engineer (Blockchain)
Junior Compiler/Virtual Machine Engineer (Blockchain)
Embedded Software Engineer/Manager
C/C++ Programmer
Senior FPGA (Design) Engineer
Senior Logic Designer/Manager
职缺传送门： https://blog.skymizer.com/jobs2019/
履历请寄到： [email protected]
## 征才公司/统编 ##
Skymizer :http://www.skymizer.com/
台湾发展软件科技股份有限公司/ 54309531
## 征才连结 ##
https://blog.skymizer.com/jobs2019/
## 关于我们 ##
Skymizer 是顶尖的编译与虚拟化技术团队，帮助客户建立各式的虚拟机与编
译器，增加软件效能、缩短 time-to-market 时间；目前我们已与世界级的
公司合作，一起开发供深度学习 (deep learning) ASIC 使用的编译器，与
新一代区块链上的智能合约 (smart contract) 所使用的虚拟机。除了内部
产品，也积极开发及参与 Open Source 的专案。我们热爱技术、想透过我们
的双手让软件界变得更好，为此，需要你的加入！
## 关于工作 ##
在 Skymizer，你可以钻研最先进的技术，从创造当中得到十足的快乐；享受
推理解谜的迷人乐趣，并将之发挥到淋漓尽致。最棒的是，你将和许多科技
狂热的强者一起共事与学习，一起创造下一代的 Compiler 工具与技术。了
解未来最好的方式就是和一群神人一起创造它，你会与一些怪才与技术狂热
者一起工作。
## 职缺一览 ##
Senior Compiler/Virtual Machine Engineer (Blockchain)
Responsibilities:
* Design and implement virtual machines for blockchain applications
* Design and build compilers for Domain Specific Language
* Design and implement new languages for blockchain applications
Requirements:
* Mastery over C and C++
* Familiar with LLVM framework
* Familiar with UNIX system programming
* Familiar with Open Source Culture
* Deep understanding of compiler, virtual machine, and runtime
Bonus:
* Familiar with Ethereum
* Familiar with any consensus protocol (e.g. Tendermint, Stellar)
Junior Compiler/Virtual Machine Engineer (Blockchain)
Responsibilities:
* Enhance existing compilers and virtual machines
for blockchain applications
* Design and Implement virtual machine components
* Design and implement static analysis tools and compiler
optimization passes
Requirements:
* Familiar with C and C++
* Deep understanding of Computer Science fundamentals
* An understanding of compiler and virtual machine
Bonus
* Experienced with UNIX system programming
* Experienced with LLVM framework
* Experienced with Ethereum
* Experienced with several consensus protocols (e.g. Tendermint, Stellar)
* Experienced with Open Source Culture
Embedded Software Engineer/Manager
Responsibilities:
* Design & develop easy-to-port deep learning runtime for variant customer
* Develop neural network SDK or toolchain for specific platform with MCU or
application processor
* Develop neural network model quantization flow
* Customize runtime, SDK and toolchain for different targets of customers
* System analysis of features, performance, problems
* Lead team members and projects (for manager position)
Requirements:
* Familiar with deep learning inferencing
* Ablility to build & port Deep Learning SDK, software stack for variant
platforms.
* Experience in RTOS application development
* Experience in linux driver development
* Experience in MCU / DSP usage.
* Good knowledge about MCU/embedded debugging.
C/C++ Programmer
Job Statement:
C/C++ Programmer is responsible for designing , developing , testing ,
deploying, maintaining software
* Build up ONNC runtime library
* Porting PyTorch to ONNC
Job Description:
Master over C and C++ programming
Familiar with Unix environments, including but not limited on Ubuntu,
CentOS,MacOSX, and FreeBSD.
Familiar with Open Source Culture
Senior FPGA (Design) Engineer
Job Statement:
The Senior FPGA (Design) Engineer will work at the system architecture level
in multiple areas of the system as an expert in one or more significant
technology domains and will serve as a technical expert in designing,
developing, and testing software for optical transport cards using FPGAs
(embedded processors) that carry a variety of data types.
Job Description:
Responsibilities:
* Design, development and test of software for deep learning accelerators
using Field Programmable Gate Arrays (FPGAs)(with embedded processors)
* Position involves writing code in Register Transfer Level (RTL)
and system integration for FPGA’s
* The position requires interaction with other System, Hardware, Firmware,
and Software developers.
Requirements:
* Preferred Degree Qualifications: Bachelor of Science (BS) or Master of
Science (MS) Degree in computer engineering or electrical engineering
* Preferred Years of Experience: BS+ (8 to 15) years, MS+(5 to 12) years
* Previous experience with Large FPGA, ASIC, or Application Specific
Standard Product (ASSP) designs or previous experience verifying complex
* Application Specific Integrated Circuits/Field Programmable Gate Arrays
(ASICs/FPGAs) using C/C++ or System Verilog
Senior Logic Designer/Manager
Self-motivated character and can work under pressure to achieve the goal.
Good communication and teamwork experience/skills
Flexibility to perform different roles throughout the project and
continuously upgrade your skills
You will also be:
* Design and developing of functional units of NN with RTL.
* Integrating a NN SoC at logic/RTL level
* Architecting a NN architecture for deep learning
* Performing all aspect of logic-design flow
Qualifications:
* Experienced with RTL/logic design
* Passion with logic design and architecture
* Passion with AI
* MS or PhD degree of EE/CS, or related background
职缺传送门： https://blog.skymizer.com/jobs2019/
## 公司地址 ##
台北市内湖区瑞光路408号12F-2
## 公司员工是否自备工作工具 ##
否
## 薪资 ##
月薪 60000 ~ 150000 元，薪资保障 14 个月。股票或股票选择权另议。
## 上班时间 ##
10:00~19:00 表定八小时，可弹性调整（早上班就早下班，晚上班就晚下班
中间休息时间自行决定）
## 平均每周工时 ##
8*5=40小时
## 加班费制度 ##
如有加班比照劳基法给予加班费或依个人意愿选择补休。
我们重视效率远胜于工时，公司并不鼓励加班。
## 员工福利 ##
* 弹性的上下班时间，自由的工作环境与风格。
* Skymizer 就是你自己的公司，你可以把环境打造你喜欢的舒适样子
* 护眼的双萤幕、最顶级的升降桌与人体工学椅，自行挑选的鼠标与键盘，还
有你想看就可以买的书。
* 每年健康检查及团体保险。
* 我们还蛮常出游的，以及有事没事就会一起玩桌游，就算没有加入我们，还
是欢迎一起来打桌游！
* 工作满一年即给予特休 14 天，每多任职一年会多一天。特休按在职比例计
算，于每年初预先发放，未满一年亦同。
* 弹性休假：遇到连假补班日不须补班，并且每年额外享有 4 天可自由安排的
弹性休假。
* 每年 3 天全薪病假。
* 同性伴侣注记视同登记，同享婚假、产假/陪产假、家庭照顾假…等。
* 有贡献就要有收获！我们会让最有贡献的人才有最大的回报。
* 公司有猫，[住在 RD 部门的猫] https://www.facebook.com/hachu.cat/
期待你来认识我们，简历请寄到 [email protected]。