课程名称︰数位系统设计
课程性质︰必修
课程教师︰欧阳明
开课学院：电机资讯
开课系所︰资讯工程
考试日期（年月日）︰2011/11/16
考试时限（分钟）：180
是否需发放奖励金：是
（如未明确表示，则不予发放）
试题 :
1. Use the K-map method to find the minimized sum-of-product expression for
each F:(8%)
(a) (4%) F(W,X,Y,Z) = ΠM(0,1,2,5,8,9,10,15)*ΠD(7,13,14)
(b) (4%) F(A,B,C,D,E) = Σm(0,2,4,8,9,11,13,15,18,20,22,25,29,31)
+Σd(6,10,19,23,27)
2. Harzards in circuit design: (12%)
(a) There are two kinds of static hazards, what are they ? Give an
example of a static hazard and explain how to avoid it. (8%)
(b) Give an example to illustrate when will a dynamic hazard occur?(4%)
3. Realize an one-bit full adder using a 3-to-8 line decoder as Fig.1 below and
(a) Two OR gates. (5%)
(b) Two NOR gates. (5%)
Fig.1 : A 3-to 8 Line Decoder
┌─────┐
│ │→ y0 = a'b'c'
│ │→ y1 = a'b'c
a →│ 3-to-8 │→ y2 = a'bc'
│ │→ y3 = a'bc
b →│ line │→ y4 = ab'c'
│ │→ y5 = ab'c
b →│ decoder │→ y6 = abc'
│ │→ y7 = abc
└─────┘
4. If the ROM in the hexadecimal to ASCII code converter of Figure is replaced
with a PAL, give the internal connection diagram. (20%)
Figure : http://i.imgur.com/COk1QTA.png?1
5. This is an optimal implementation of master-slave flip-flop. It only
requires 7 2-input gates. Please draw the waveform for QA, QB, QC according
to the waveform of the clock and b of the following circuit. Assume QA, QB,
and QC = 0 initially. (20%)
Figure : http://i.imgur.com/QgcmajR.png
6. (20%) (you can choose either (a) or (b) below, but not both)
(a) A sequential circuit has two D flip-flops A, B, and two input X, Y.
The circuit is described by the following input equations :
DA = X'A + XY, DB = X'A + XB, Z = XB , where X' is the
compliment of X. Please first draw the circuit and derive the state table, and then
draw the state diagram.
(b) Please design the synchronous schematic of the given state diagram
(a) by using positive edge clock trigger JK flip-flop, state
diagram (b) by using positive edge trigger clock D flip-flop.
Figure : http://i.imgur.com/02idES4.png
7. Please design the circuits as follows:
(a) Using D type latch to design a one-bit memory cell with a Data IO
signal, a AddressEnable signal and a RW signal, which store the
data at Data IO to memory when both RW signal and AddressEnable
high. Output the stored data to Data IO when RW is low and Address.
(5%)
┌────┐
│ │
Write/Read →│ Memory │
│ │←→ Data In/Out
AddressEnable →│ Cell │
│ │
└────┘
(b) Design a schematic for Z = ABC + AD + C'D using only 2-input NAND
gates. Use as few gates as possible. (5%)
(c) Implement ABDE' + A'B' + C using three 3-input-NOR and one
2-input-NOR gates. Note: your input can be A, A', B, B', C, C', D,
D', E and E' but output is F. (4%)
8. Consider the two Boolean functions, F1 and F2, given by the following truth
table:
│x y z │F2 F2' F1 F1'
─┼───┼───────
0│0 0 0 │ 0 1 0 1
1│0 0 1 │ 1 0 0 1
2│0 1 0 │ 0 1 0 1
3│0 1 1 │ 0 1 1 0
4│1 0 0 │ 1 0 0 1
5│1 0 1 │ 0 1 1 0
6│1 1 0 │ 0 1 1 0
7│1 1 1 │ 1 0 1 0
9. Consider a simple car alarm system involving three sensors. "G" is 0 or 1 if
the ignition is OFF or ON, respectively. "D" is 0 if all doors are CLOSED
and 1 if any door is OPEN. "L" is 0 or 1 if the headlights are OFF or ON,
respectively. The output "ALARM" should be 1 (HIGH) in the following cases:
1. The headlights are ON while the ignition is ON.
2. Any door is OPEN while the ignition is ON.
(a) Build the truth table (G, D, L ALARM), construct the K-map, and
derive the simplified sum-of-products expression for ALARM. (4%)
(b) Implement the ALARM function using exactly four 2-input NAND gates.
Do not use complemented inputs. (4%)