In a single-cycle datapath design of MIPS architecture, which of the following description is correct?
(a) The data flow of R-type instructions does not go through the data ememory.
(b) The data flow of SW goes through all components in a clock cycle.
(c) The data flow of LW goes through all components at most once in a clock cycle.
(d) The data flow of J-type instructions goes through all components.
答案: (a) (b)
想问(b)，SW的data flow如下图
https://imgur.com/YchMDiA
没有经过branch的那个adder，那这样应该就不是go through "all" components了吧?
另外想请问(c)错是因为把data从Memory write back回Register File，这样就会经过Register File"第二次"，所以"at most once"是错的，这样子吗?
图片来源:
https://image.slidesharecdn.com/lec-12-15mipsinstructionsetprocessor-150916045626-lva1-app6892/95/lec-1215-mips-instruction-set-processor-24-638.jpg?cb=1442379456