各位年薪百万大家好
小弟私立学店EE
这礼拜收到台中后里CP值破表的职务邀请
依他们要求的寄了英文履历后
HR打电话来做了简单的phone interview约15-20分
但都没提到此份职缺的相关讯息
并跟我说主管出差回来后会再跟我联络后续
想请教各位前辈这个PYE是什么样的工作呢？
Product Yield Enhancement (PYE) Engineer
Date: Aug 20, 2018
Location: Taichung, TXG, TW
Description:
Req. ID: 121945
As a Product Yield Enhancement (PYE) Engineer for Micron Technology, Inc., you
will work with a team responsible for taking next generation devices from des
ign to mass production. You will focus on failure analysis of test, quality,
and RMA failures, allowing for enhanced product reliability, rapid production
ramp and early time to market. Your primary areas of responsibility will util
ize fault isolation with a combination of electrical and physical characteriza
tion techniques combined with data analysis to identify physical defects intro
duced by process level or assembly step. Additionally, you will be responsibl
e for communicating and coordinating failure analysis findings with Management
, Product, Process, Assembly and Quality Assurance groups.
Responsibilities include, but are not limited to, the following:
Perform Failure Analysis and Fault Isolation
Operate uMate/Nextest bench test platforms
Operate iPHEMOS and IREM emission tools
Characterize or model backend test, Quality, and RMA fail signatures
Extensive understanding of the physical and logical design of the part
Use layout/schematic to aid in fault isolation and fail signature modeling
Understand various PFA techniques available for de-processing failures
Understanding Fabrication Process and Package Assembly
In depth understanding of CMOS process fabrication levels, steps and methodolo
gies
Knowledge of the steps and details involved in the package assembly flow
Understand reliability concerns that can cause delayed breakdown fail signatur
es
Extensive expertise with process and assembly related defects as well as their
causes and effects
Provide Clear and Comprehensive Fail Signature Reports
Understand probe, backend test and qualification flows
Generate organized and timely failure analysis reports with clearly communicat
ed causes and effects
Use JMP for analyzing and preparing data
Perform fab, probe and backend data extractions to provide supplemental data
Successful candidates for this position will have:
Excellent problem-solving and analytical skills
Strong grasp of concepts regarding thorough investigative procedure
Computer aided layout and schematic experience
Semiconductor process coursework and/or experience
UNIX and Programming experience
Experience working in teams and ability to work well with others
Solid GPA
Work experience in related field through co-op, internship, or projects
Course work in VLSI design and semiconductor device physics (Preferred)
Good communication skills
Self-motivation and enthusiasm
work shift
Education:
Bachelor’s Degree in Electrical or Computer Engineering
We recruit, hire, train, promote, discipline and provide other conditions of e
mployment without regard to a person's race, color, religion, sex, age, nation
al origin, disability, sexual orientation, gender identity and expression, pre
gnancy, veteran’s status, or other classifications protected under law. This
includes providing reasonable accommodation for team members' disabilities or
religious beliefs and practices.
Each manager, supervisor and team member is responsible for carrying out this
policy. The EEO Administrator in Human Resources is responsible for administra
tion of this policy. The administrator will monitor compliance and is availabl
e to answer any questions on EEO matters.