我今天尝试将elevator.v 读进去以后synthesis
再将它用write des 写成elevator2.v档
但是我再将elevator2.v档读进来时 出现以下错误:
Error : The sub-module "DVL_BUF" is not defined in the module "elevator"
整个过程如下:
[ckmarkoh@hebe ~/SOCV/pa1 ]$ ./logicSim.ref-32
QuteRTL> rea de ./elevator_design/elevator.v
> Parsing Verilog File : /home/ckmarkoh/SOCV/pa1/elevator_design/elevator.v
...
==================================================
==> Total 1 Module(s)
==> Top Module : elevator
DESIGN @ elevator> syn
=== Start Synthesis ...
> Synthesizing Module : elevator ...
=== Cell Collection and Naming ...
=== Set CktModule ...
==================================================
==> Total 1 Module(s)
==> Top Module : elevator
DESIGN @ elevator> write des elevator2.v
Write design start...
Write design successfully!!
DESIGN @ elevator>
DESIGN @ elevator> q -f
[ckmarkoh@hebe ~/SOCV/pa1 ]$ ./logicSim.ref-32
QuteRTL> rea des elevator2.v
> Parsing Verilog File : /home/ckmarkoh/SOCV/pa1/elevator2.v ...
==================================================
==> Total 1 Module(s)
==> Top Module : elevator
Error : The sub-module "DVL_BUF" is not defined in the module "elevator"
[ckmarkoh@hebe ~/SOCV/pa1 ]$
请问为何会发生这种Error?