代po勿站内信
<月薪20万起～美商Cisco思科台湾全职 (Full Time) 职缺>ASIC 技术主管
～月薪新台币20万元起~
申请截止日：2018年9月30日
此次主要招募对像为ASIC 技术主管, 请投递中英文履历至
Cisco思科人力资源大中华区联络人
Sarah Shen| [email protected] | +86 21 2407 3253
工作地点：台北市11052信义路四段460号12楼
<薪资福利>
薪资: 月薪新台币20万元起~12个月
奖金：视个人绩效与公司营运
特休假：一年12天（带薪病假24天另计）, 生日假1天，公益假5天，紧急事假4周
加班费制度：比照劳基法
<工作型态>
上班时间：周休二日，弹性工作制
管理责任：负担技术管理责任
最低资格:
*需要3年以上ASIC 硬件设计经验，熟悉Verilog RTL 语言
*熟悉IC 设计流程，从功能规格，实现，验証到量产
*英文听、说流利。
*有以太网络经验和TCP/IP 经验佳
*有验证System verilog 或 UVM 经验佳，但非必须
*电机或资讯硕士
What You'll Do
The INSBU nexus 9k group is looking for an experienced Technical Leader to drive existing projects and engage in new development of our Nexus 9K family. The ideal candidate will have an ASIC design ba
It used to be that high-speed packet forwarding was performed in dedicated ASIC designs. These days we are looking to make those ASICs more general and programmable. P4 has been proposed as a domain-s
It used to be that high-speed packet forwarding was performed in dedicated ASIC designs. These days we are looking to make those ASICs more general and programmable. P4 has been proposed as a domain-s
Who You'll Work With
Who You'll Work With
INSBU developed the Nexus 9000 line of data center switches and Application Centric Infrastructure, Cisco’s premier datacenter SDN solution. Our team within INSBU is responsible for driving integrati
INSBU developed the Nexus 9000 line of data center switches and Application Centric Infrastructure, Cisco’s premier datacenter SDN solution. Our team within INSBU is responsible for driving integrati
INSBU develops high-performance switches for the data center and for the cloud. You will be working with the team that develops the ASICs at the heart of each of these switch products. There are only
INSBU develops high-performance switches for the data center and for the cloud. You will be working with the team that develops the ASICs at the heart of each of these switch products. There are only
Who You Are
Cisco INSBU is looking for a passionate ASIC Designer to join our R&D team. This role involves working on cutting-edge high performance ASIC design from specification to RTL implementation. The new me
hardware and network OS developers.
· Develop network processing ASIC architecture and micro architecture specification
· Design high performance and high quality ASIC design from specification to RTL implementation
· Perform ASIC verification, synthesis, timing analysis IP integration
· Participating system/board level bring up, debugging and support
Experience Required
· 3 years or more networking ASIC experience
· Strong tracking record of ASIC design from concept to mass production
· Hands-on experience on Verilog HDL coding and verification
· Experience of high performance ASIC design from specification to system bringing up
· Ethernet and TCP/IP networking concept and protocols knowledge
· Knowledge of System Verilog and UVM verification methodology
· Highly motivated, positive, detail oriented and responsible
· Highly motivated, positive, detail oriented and responsible
· Good team player and good communication skills
· MSEE/MSCS
· MSEE/MSCS