长期工读, 6个月以上, 视专案调整
职务类别： 数位IC设计工程师
工作待遇： 依公司规定
工作性质： 长期工读 限在学生
上班地点： 新竹市埔顶路25号
上班时段： w1-w5 0900-1800 皆可排班，每周需满20小时，亦可上满40小
可上班日： 两周内
需求人数： 1至5 人
Join the world-class team to develop next generation high speed SME
networking chip. The candidate will have hands-on experience to work with
senior designers on all aspects of IC-design. In addition, the candidate will
have an opportunity to expose to the latest state-of-art design technology
and methodology. The candidate will also involve in
‧Design/Verification flow for networking SoC
‧Work with team members to execute design verification plan
‧Get familiar with tool chain for digital IC design flow
‧Help to trouble-shooting and root-cause design issue
Requirements:
‧Undergraduate (senior year) or 1st/2nd year of graduate study in Electrical
Engineering or Computer Science.
‧Familiar with UNIX/LINUX platform and logic design are required
‧Familiar with any of the following will be a plus.
A)Networking background
B)Verilog and System Verilog knowledge
C)SHELL/PERL scripting
D)C/C++ programming
工作经历： 不拘
学历要求： 硕士班以上 限在学生
科系要求： 电机电子工程相关、资讯管理相关、资讯工程相关
语文条件： 英文