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作者: suspect1 () 看板: Electronics
标题: [问题] SR latch
时间: Thu Jun 21 22:01:53 2018
板上的大大可以解释一下这个考题的意思吗？
a SR latch implemented with 2 Nand gates
(1)changes in 2 outputs always take place with time difference of a gate
delay ? (True or False)
(2)It takes shorter time to set Q to 1 than reset Q to 0 (True or False)