[理工] 计组 pipline clock cycle time

楼主: jerry900287 (卤蛋)   2017-09-24 14:09:31
问题如图: https://i.imgur.com/MTG1Ok2.png
老师的算法是
IF stage : 15(PC) + 50(IM) = 65
ID stage : 20(Control) + 10 (Mux) + 15(Pipeline register) = 45
EX stage : 20(Forwarding unit) + 10(Mux) + 30(ALU) + 15(Pipeline register)=75
MEM stage : 50(DM) + 15(Pipeline register) = 65
WB stage : 10(Mux) + 20(Register File) + 15(Pipline Register) = 45
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我的写法是说
IF stage : 15(PC) + 50(IM) + 15(Pipeline register) = 80
ID stage : 20(Control) + 10 (Mux) + 15(Pipeline register) = 45
EX stage : 20(Forwarding unit) + 10(Mux) + 30(ALU) + 15(Pipeline register)=75
MEM stage : 50(DM) + 15(Pipeline register) = 65
WB stage : 10(Mux) + 20(Register File) = 30
问题(一) : 为什么IF stage 不用再加pipeline register的时间?
问题(二) : 关于pipeline的观念
我印象中 每做完一个stage 会写入Pipeline Register
所以 IF ID EX MEM 都会写入右边的Pipeline Register
只有WB 没有Pipeline Register 要写入才对
但是这题为什么要算?!
感谢大大们QQ
作者: gugu40841   2017-09-24 16:24:00
一Clock时间点结束时会停在pipeline reg.前,下一Clock来才开始自pipeline reg.跑到下一pipeline reg.前

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