[理工] 计组 pipeline 问题

楼主: boy00114 (ponny)   2016-08-26 19:11:17
今天唸到这个问题
三年前有人在板上问过了
但是我看了还是搞不太懂
请各位帮忙指点一下各个选项要表达的意思
如果有张凡课本可直接参考上册P437.P438的练习题
题目:A group of students have been debating the efficiency of five-stage pipel ine when one student pointed out that not all instructions are active in every stage of the pipeline.After deciding to ignore the effects of hazards,they ma de the following five statements.Which ones are correct?
1.Allowing jumps,branches,and ALU instructions to take fewer stages than the f ive required by the load instruction will increase pipeline performance under all circumstances.
2.Trying to allow some instructions to take fewer cycles does ont help,since t he throughput is determined by the clock cycle;the number of pipe stages per i nstruction affects latency,not throughput.
3.Allowing jumps,branches,and ALU operations to take fewer cycles only helps w hen no loads or stores are in the pipeline,so the benefits are small.
4.You cannot make ALU instructions take fewer cycles because of the write-back of the result,but there is some opportunity for improvement.
5.Instead of trying to make instructions take fewer cycles,we should explore m aking the pipeline longer,so that instructions take more cycles,but the cycles are shorter.This could improve performance.
ANS:2 and 5 are correct
作者: kyuudonut (善良老百姓)   2016-08-26 23:24:00
2. throughput 被 cycle time 决定呀5. 管线越多级,"理论"上时间就会减少好几倍
作者: aa06697 (todo se andarà)   2016-08-27 01:29:00
1. load 仍要五个cycle所以并不会变 而要取最多cycle数所以performance不变 2. 总时间为(IC - 1 + stage数)*cycle time 一般IC极大于stage数所以忽略stage 所以总体效能(throughput)会取决于cycle time 降低stage数只会影响单一instruction的latency 3. ALU没办法减少cycle 因为他一定要write back(完整五个stage) 4. 前面是对的 正是因为没办法减少 所以仍会取最长的5个stage (我是觉得有点争议啦...硬要说的话 把cycle time 减少 performance不就变好了...)5. cycle变多所以cycle time变短 所以performance提升补充一下5 原先5个stage的时间拆成更多stage 所以一个stage(cycle time) 时间变短
楼主: boy00114 (ponny)   2016-08-27 11:29:00
我了解了谢谢楼上两位大大!

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