[理工] [计组] 内存与cache

楼主: jinniw43805 (Mg镁)   2015-07-27 18:17:18
Assume the following 8-bit address sequence generated by the microprocessor
The cache uses 4 bytes per block. Assume a 2-way set assocative cache design
the uses the LRU algo. (with a cache that can hold a total of 4 blocks).
Assume that the cache is initially empty.First determine the TAG,SET,BYTE
OFFSET fields and fill in the table above. In the figure below ,clearly mark
for each access the TAG,Least Recently Used(LRU) ,and HIT/MISS information
for each access.
题目表格如下:
,b6uUEAY
答案如下:

我的想法:
题目提到总共有4个blocks ,所以我们不是需要4=2^2 ,两个bits去表示是哪个block嘛?
答案Index那边只有一个表示,觉得有点小小奇怪。感谢各位先进了!
作者: A4P8T6X9 (残废的名侦探)   2015-07-27 22:08:00
2way set,代表一个set两个block,总共两个set。所以index只要1个。

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