[公司名称] Sintegra Inc.
[职缺] Physical Design Engineer (APR) – Hsinchu
[工作内容]
* ASIC/SoC Physical Design implementation from Netlist to GDSII
* Floorplanning and Power Planning
* Placement and optimization
* Clock Tree Synthesis (CTS)
* Routing and post-route optimization
* Static Timing Analysis (STA) and Timing Closure
* Setup/Hold analysis and optimization
* ECO implementation and timing fixes
* Signal Integrity (SI) analysis
* IR Drop / EM analysis and optimization
* Physical verification including DRC/LVS
* PPA (Power, Performance, Area) optimization
* Collaborate with RTL, STA, DFT and other design teams
* Support final design signoff and tapeout
[工作地点] 竹北
[职务需求]
* 2–6 years of hands-on ASIC Physical Design / APR experience
* BS/MS degree in Electrical Engineering, Electronics Engineering, Computer
Engineering or related field
* Good understanding of the complete Physical Design flow
* Hands-on experience in one or more areas including Floorplan, Placement,
CTS, Routing, STA, Timing Closure and ECO
* Experience with advanced semiconductor process nodes preferred
* Good understanding of timing, clocking, congestion and power optimization
* Strong debugging and problem-solving skills
* Ability to work independently and collaborate with global engineering teams
[待遇] 年薪台币 200万 ～ 250万元
[联络方式]
意者请将英文 CV 寄至： [email protected]