[公司名称]
Analog Device ( ADI , 雅德诺半导体)
[公司网站]
https://www.analog.com/en/index.html
[公司地址]
No. 223号, 台北市松江路223号
[公司介绍]
世界第二大类比设计场,不久前并购第三大美信
坐二望一准备飞天 （拍谢国文没学好）
有兴趣请寄信到
[email protected]
或是站内信
谢谢
Job Title: Senior Analog Design Engineer
In this position, your primary focus will be signal chain and sub blocks desig
n, including ADC, DAC and various Amplifiers, you will also have opportunities
to participate in the design of power converters and other supporting circuit
ry across CMOS/BCD process nodes.
Responsibilities
‧ Participate in cutting-edge analog and mix-signal IC development.
‧ Work with cross functional teams and cross sites, contribute to the be
st
sign topology and methodology for a given application.
‧ Develop the product objective specification document that includes di
e
e estimation, package selection, pin descriptions, block diagrams and all aspe
ct of IC electrical specifications.
‧ Model and Design from beginning to end which includes top level modeli
ng
chematic captures, and simulations.
‧ Select the appropriate process that maximizes the value of the final I
C
duct with the best engineering trade-offs.
‧ Oversee the IC layout and provide guidance to the demo-board PCB layou
t.
‧ IC bench verifications, failure analysis and yield improvements suppor
t.
Required Skills and Qualifications
‧ Master or PHD in Electrical Engineering with experience in analog/mixe
d-
nal IC development
‧ Strong skills in CMOS analog design and layout
‧ Strong s-domain and z-domain analysis skills
‧ Organized, thorough, and detail-oriented with strong communication ski
ll
‧ Self-motivated with strong analytical and problem-solving skills
‧ Ability to work with a sense of urgency and thrive in a dynamic enviro
nm
Preferred Skills and Qualifications
‧ Knowledge of discrete-time and continuous-time signal processing
‧ Experience in system and behavioral modeling
‧ Experience in Delta-Sigma ADC/DAC, SAR ADC and Power Amplifiers.
‧ Good silicon debug skills
‧ Understanding of layout
‧ Understanding of reliability concerns
‧ Different CMOS processes and geometry nodes