代PO, 勿站内信!!
<工作地点>
台北市11052信义路四段460号12楼
履历请寄：Jackie Su ([email protected])
<薪资福利>
薪资: 16~20万*12个月+ESPP+分红 (月薪视个人能力调整)
分红：视个人绩效与公司营运
特休假：到职第一年12天, 之后逐年累加1天, 弹休另计
全薪病假：10天
另有生日假1天, 公益假5天, 紧急事假4周(皆为全薪)
<职缺>
○ Senior ASIC designer
< Experience Required >
‧ 5 - 10 years in ASIC experience. Network ASIC experience is a plus.
‧ Strong tracking record of ASIC design from concept to mass production
‧ Hands-on experience on Verilog HDL coding.
‧ Experience of high performance ASIC design flow from specification to
system bringing up
‧ Highly motivated, positive, detail oriented and responsible
‧ Good team player and good communication skills
‧ MSEE/MSCS
○ Senior ASIC verification
< Experience Required >
‧ 5 - 10 years in ASIC design verification.
‧ Hands-on experience on Verilog HDL verification
‧ Experience of high performance ASIC design flow from specification to
system bringing up
‧ Knowledge of System Verilog and UVM verification methodology
‧ Highly motivated, positive, detail oriented and responsible
‧ Good team player and good communication skills
‧ MSEE/MSCS