Job Description
1 IC封装的基板设计及布局
1.1 IC封装型式涵盖覆晶封装及打线型封装，单芯片封装及多芯片封装
1.2 基板层数涵盖2层至20层以上。有4层 (1-2-1) 板以上设计经验为佳
1.3 最佳化高速讯号 (DDR, SerDes, PCIe...) 的线路布局
1.4 非常了解基板设计规范及封装制程规范
2 协同IC及印刷电路板的设计
2.1 提供 bump/ball 的配置建议给 IC/PCB 设计工程师以最佳化 Chip-Package-PCB
的设计
3 其他
3.1 专案管理
3.2 营运管理协助
Requirements
1 正直乐观、主动积极、认真负责
2 具三年以上IC封装基板布局设计相关工作经验
3 具有 Cadence APD 实际操作经验
4 具大学以上学位且有修习过科学或工程相关课程者为佳.
资深工程师者不受此限
Company Offers
1 具市场竞争力的薪资及营运绩效奖金
2 畅通的升迁管道以及不受限的职涯发展
3 年度旅游补助津贴
上班时间: 星期一至星期五. 8:30AM - 17:30PM， 15分钟上下班弹性时间
上班地点: 台北景美
月薪: NTD50K - NTD100K
履历请直接寄至: [email protected]
公司网站: sarcinatech.com
Job Description
1 IC package substrate design and layout
1.1 Package type includes flip-chip and wirebond. Single die design and
multi-die design
1.2 Substrate layer count from 2 layers to 20+ layers. Preferred experience
is at least 4 layers (1-2-1)
1.3"High-speed (DDR, SerDes, PCIe...) signal routing optimization"
1.4 Good knowledge in substrate layout design rules and package assembly
design rules
2 Chip-Package-PCB co-design
2.1 Review die bump assignment and BGA ball assignment to provide suggestions
to optimize the design
3 Other assignments and tasks
3.1 Project management
3.2 Operation assistance
Requirements
1 "Enthusiastic, proactive, and responsible. Has integrity"
2 At least 3-year working experience on IC package substrate layout
3 Hands-on experience using Cadence Allegro Package Designer (APD)
4 A bachelor degree or above in science or engineering is preferred.
Outstanding candidate without a college degree will be considered
Company Offers
1 Competitive salary and bonus
2 Unlimited career growth opportunity in company
3 Annual vacation allowance
Working Hours: Monday - Friday. 8:30AM - 17:30PM with 15 minutes flexibility
Working Location: Jingmei, Taipei"
Monthly salary: NTD50K - NTD100K
Please send your resume directly to: [email protected]
Company website: sarcinatech.com