[2019/03/16 update]
最新消息是这个新团队工作地点不侷限 (台湾/上海/美国/...)
目前也在找团队Leader, 所以我或许需要再调整下述的待遇上限,
但这真的很看人,所以我就先不改了,总之有意愿的人请不要犹豫将履历寄给我.
[公司名称] 美商超微半导体台湾分公司
[职缺名称] SDX-USB/PCIE IP design工程师
[征求条件]
工作内容
- Develop micro-architecture for USB blocks based on architectural
requirement.
- Develop RTL code for USB blocks in Verilog HDL and make sure functional
correct and
reusable for different configuration.
- Synthesis and deliver netlist that meeting timing, area and power
requirement. Help
PD on the floor planning and close timing.
- Analyze gating efficiency report to improve RTL quality.
Job Requirements:
- MS degree of EE with 10+ years working experience in ASIC Company.
- Expert of Verilog RTL design and has experience of large digital ASIC
project.
- Familiar with front-end EDA tools and flows.
- Familiar with Unix/Linux and scripts (tcl, perl, ruby and etc.)
- Fluent English on talking, presentation and writing documents.
- Work is performed with limited supervision. Strong sense of task
scheduling and
deliver on time as predetermined milestones committed to manager.
- Can solves complex, novel and non-recurring problems; initiates
significant changes to
existing processes/methods and leads development and implementation.
-Possesses specialized knowledge of computer architecture and computer
arithmetic.
- Possesses specialized knowledge of PCIE and AMBA.
- Possesses specialized knowledge of USB and Thunderbolt (a plus)..
[工作型态]
周休二日 外商管理
并上海团队密切合作
[待遇]
年薪保守预估200W NTD以上,
依照个人能力与学经历调整,
如果您够优秀, 数字可能 >> 200 (200~500)
[联络方式]
请将履历寄至 [email protected]
这是一个外商难得的RTL designer在台湾的职缺,
还有其他很不错的福利,
有兴趣想了解更多的朋友,请再私讯我