※ 引述《giorno78 (天晴)》之铭言：
: 作者: KotoriCute (Lovelive!) 看板: PC_Shopping
: 标题: [闲聊] Intel 到底怎么了? Part 2
: 时间: Wed Jul 29 19:42:41 2020
:
: https://www.facebook.com/RDinPortland/posts/3187666937992352
:
: Intel 到底怎么了? Part 2
:
: Intel为什么会找上台积电代工? 这不是一个突然的决定, 一切都是有迹可循的, 冰冻三
: 尺非一日之寒.
:
: → pp520 : 快快 我想看 Part 3 07/29 20:59
: → pp520 : 问一下 chia hong 是谁 ? 07/29 21:00
有人问 Chia-Hong 是谁，应该是下面这一位，他是第一个台大毕业的 Intel Fellow。
http://www.che.ntu.edu.tw/ntuche/cht/bulletin_content.php?id=393
2010年获选为 Intel Fellow 时台大化工官网上的简介：
简嘉宏博士 毕业于国立台湾大学化学工程学系(1982)，1986年获国立台湾大学工商管理
硕士，分别于1988年与1991年 获得美国威斯康辛大学麦迪逊校区材料科学硕士与博士学
位。目前是英特尔院士，英特尔公司SoC积体电路技术集团的技术和制造部门负责人，为
第一位来自国立台湾大学的英特尔院士(intel fellow)。
简嘉宏博士是英特尔研究员与SoC积体电路技术集团的技术和制造部门负责人。在这个职
位上，简博士管理英特尔公司所有SoC产品的32奈米和22奈米制程技术 ，包括超低功耗的
移动网络设备，netbook处理器，消耗性电子产品， 嵌入式产品，无线通信应用和 芯片
组 /图形处理器。
简博士自从 1991年加盟英特尔后，拥有多项技术及身居0.8um， 0.55μm，0.35微米，
0.25微米，0.18微米，0.13微米，90奈米，65奈米，45奈米，32奈米波特兰技术发展
(Portland Technology Development)和现在 22奈米先进的CMOS技术发展的管理职位。他
是快速热的处理（RTP）的和先进的硅沉积（ASD）的小组负责人， 工作目标在发展新型
硅化物技术，先进的gate oxide processes ，源/漏枢纽工程和磊晶硅锗 应变硅技术。
他带领的团队，率先整合 新硅化物材料，包括引入钛（0.55μm）， 钴（0.18）和镍进
入basic logic CMOS处理器。他亦是 90纳米交结积体电路部门经理，和他的团队是第一
个 在工业界成功整合low-k ILD材料应用于高功能微处理器者。他同时还是 Intel®
Atom™ processor 禆ased low-power products(英特尔 ®凌动™处理器二叉树低功耗
产品)中65奈米低功耗芯片制造技术与45奈米SoC制造技术项目经理，此项产品针对有效利
用创新的high-k/metal gate技术于SoC领先应用于工业界。
在半导体制程与积体电路领域中，简博士拥有 37项美国专利 。他已发表超过 40篇与
CMOS加工技术有关的技术 论文。获得3项 英特尔成就奖，并在2008年获颁威斯康辛大学
麦迪逊分校工程学院杰出成就奖。
http://gipo.ntu.edu.tw/p5news-3-detail.php?sn=8828
2018年回台大光电演讲时的简介(此时已是Intel Senior Fellow, 2017年时获选 IEEE Fellow, 当时担任 Intel HPC Director)。
Chia-Hong Jan is an Intel Senior Fellow and the Director of High-Performance
Computing (HPC) and System on Chip (SoC) technology integration for the
Technology and Manufacturing Group at Intel Corporation. He is responsible
for Intel’s most advanced process technology development for next-generation
CPUs used in high-performance and SoC product segments, including data
center, cloud server, desktop, laptop, notebook, tablet, smartphone,
application-specific integrated circuits, field-programmable gate arrays and
wireless communication products.
The Institute of Electrical and Electronics Engineers (IEEE) has named
Chia-Hong Jan) among its 2017 class of fellows. The honor recognizes Jan for
his leadership in developing low power logic technologies for System-on-Chip
(SoC).
Jan holds a bachelor’s degree in chemical engineering and an MBA degree from
National Taiwan University. He also earned a master’s degree and Ph.D. in
materials science from the University of Wisconsin-Madison.
Since joining Intel in 1991, Jan has held various technical and leadership
roles in the Portland Technology Development organization related to the
development of 0.8μm, 0.55μm, 0.35μm, 0.25μm, 0.18μm, 0.13μm, 90nm,
65nm, 45nm, 32nm, 22nm and 14nm advanced CMOS technology. He was the group
leader for rapid thermal processing and advanced silicon deposition
engineering, working on the development of novel salicide technology,
advanced gate oxide processes, source and drain junction engineering, and epi
SiGe technology for strained silicon. As the manager of 90nm interconnect
integration, he led the team credited with being the first in the industry to
successfully integrate low-k ILD materials for high-performance
microprocessors. He was also the program manager for the 65nm low-power
chipset process technology, and for 45nm, 32nm, 22nm and 14 nm SoC process
technology for Intel® Atom™ processor–based low-power products, including
micro-servers, tablets and smartphones, and chipsets, wireless and FPGA
products. Jan was promoted to Intel Senior Fellow, the highest technical
position at intel, in 2016.
Jan holds more than 88 patents worldwide in the field of semiconductor
manufacturing process and integration. He has authored/co-authored more than
40 technical papers related to CMOS processing technology. Jan has received
three Intel Achievement Awards (IAA) and was honored with the UW-Madison
College of Engineering’s Distinguished Achievement Award in 2008.