[问题] verilog语法问题

楼主: KAINTS (大安Eason哥)   2014-03-07 11:45:35
wire [ 3: 0] read_mux_out;
reg [ 31: 0] readdata;
readdata <= {{{32 - 4}{1'b0}},read_mux_out};
请问一下这是把read_mux_out的4 bits放在readdata 最后四位元
而readdata的前面28 bits都补0的意思吗?

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