[问题] verilog竞赛问题

楼主: Rockwho (FFForder)   2010-02-05 18:06:20
s1:begin
...
a = a + 1;
if(a == ...)
begin
...
...
end
...
end
模拟出来的值是对的,但以reg观念来想似乎应该要再等一个cycle
如果以真实合成出来的正确性来看,我是否该再等一个state再做判断?
请指教~

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