写在前面:
Intel为了对飙AMD CPU的核心数
并不是第一次使用胶水(Cascade Lake-AP)
多了一个Die自然核心数,内存和PCIE通道数倍增
良率可能就...
ICX最多38C已经钉死
ICX下一代SPR要抗击米兰甚至热那亚
势必要出招(没128C, 至少意思要到)
目前看资料不像是黏大Die
TOM's Hardware原文连结:https://reurl.cc/EzAZ7K
Two-Die Xeon? Leaked Sapphire Rapids Photo Appears to Show Chiplets
2Die Xeon? 流出的Sapphire Rapids(CPU代号)照片似乎显示了Chiplets
A member of ServeTheHome forums has published what he claims to be the first
photos of Intel's Xeon Scalable 'Sapphire Rapids' processor. If the images
are legitimate, they may shed some light on the design of the CPU and may
indicate that it does not use a large monolithic die, but actually carries
two dies.
ServeTheHome 论坛的成员 发布了他所谓的英特尔Xeon Scalable“Sapphire Rapids”处
理器的第一张照片。如果影像是合法的，则它们可能会为CPU的设计提供一些启示，并可能表明它
没有使用大型的单片芯片，但实际上带有两个芯片。
The photos depict an LGA processor with a metallic heat spreader carrying an
'Intel Confidential' mark, which indicates that this is a pre-production chip
meant for testing and evaluation. Another engraving indicates a rather
moderate 2.0 GHz frequency of the CPU which is something to be expected from
an early sample. Also, since the processor is a pre-production sample, it has
a four-character stepping: QTQ2. Since the device does not look like an
existing Intel processor, it could well be a sample of Intel's upcoming
Sapphire Rapids.
这些照片描绘了带有金属散热器(有case非裸晶)的LGA处理器，该散热器带有
“ Intel Confidential”标记，表明该芯片是用于测试和评估的预生产芯片。另一个刻图
表明CPU的频率相当中等，为2.0 GHz，这是早期样本所预期的。同样，由于处理器是生产
前样品，因此它具有四个字符的步进：QTQ2。由于该设备看起来不像现有的英特尔处理器
，因此很可能是英特尔即将推出的SPR的样本。
The front side of the alleged Sapphire Rapids processor reveals a rather
intriguing detail. The heat spreader of the CPU has two bulges of about the
same size. Intel's contemporary CPU heat spreaders do feature a number of
convexities, but there is always one main 'bump' above the main die. Two
bulges may indicate that Intel uses two processor dies for Sapphire Rapids
instead of one monolithic die.
所谓的SPR处理器的正面显示了一个相当有趣的细节。CPU的case有两个大小相
同的凸起。英特尔现代的CPU case确实具有许多凸点，但在主芯片上方始终有一个主“
凸点”。两个凸起可能表明英特尔为蓝宝石急流使用了两个处理器芯片，而不是一个整体
芯片。
The back side of the CPU looks typical for Intel's latest server processors
with its land grid array split into two domains. Meanwhile, there are two
identical sets of capacitors in the middle of the package, which supports the
theory that Intel's Sapphire Rapids is indeed a multi-chip-module (MCM)
carrying two dies interconnected using one of Intel's latest technologies
(e.g., EMIB). By contrast, Intel's monolithic dies have one set of capacitors
on the back of their packaging.
对于英特尔最新的服务器处理器，CPU的背面看起来很典型，其land grid array分为两块
(如果你看过一般Intel server CPU的背面, 就会比较理解这在讲什么)
。同时，封装中间有两组相同的电容器，这支持以下理论：英特尔的Sapphire Rapids实
际上是一个多芯片模块（MCM），带有两个芯片，这些芯片使用英特尔的最新技术（例如
EMIB）互连。 。相比之下，英特尔的单芯片在其封装的背面只有一组电容器。
Using an MCM — or chiplet — design has a number of advantages when it comes
to development and manufacturing. For obvious reasons, it is easier to
design, emulate, and debug smaller chips. It is also easier to hit decent
clocks and yield levels with smaller dies. On the other hand, large
monolithic dies work more efficiently as internal interconnections are always
faster than off-chip interconnects.
在开发和制造中，使用MCM（或小芯片）设计具有许多优势。出于显而易见的原因，设计
，模拟和测试较小的芯片更加容易。较小的裸片更容易达到良好的clock和良率。另一方面
，大型单片芯片的工作效率更高，因为内部互连总是比片外互连更快。
As a rule, Intel does not comment on leaked information about its unreleased
products, so do not expect the company to confirm or deny any facts about its
Sapphire Rapids processor beyond what is has already been revealed.
通常，英特尔不会对未发布产品的泄漏信息发表评论，因此不要指望该公司证实或否认有
关Sapphire Rapids处理器的任何事实。
So far, Intel has publicly confirmed that its Sapphire Rapids processors will
use the Golden Cove microarchitecture that supports Intel’s Advanced Matrix
Extensions (AMX) as well as AVX512_BF16 and AVX512_VP2INTERSECT instructions
that are particularly well suited for datacenter and supercomputer workloads.
到目前为止，英特尔已经公开确认其SPR处理器将使用支持英特尔高级矩阵扩展（
AMX）以及特别适合数据中心和超级计算机工作负载的AVX512_BF16和
AVX512_VP2INTERSECT指令的Golden Cove微架构。
In addition to microarchitectural innovations, the new CPU will feature a
DDR5 memory controller (enhanced with Intel’s Data Streaming Accelerator,
DSA), the PCIe 5.0 bus with a 32 GT/s data transfer rate that is enriched
with the CXL 1.1 protocol to optimize CPU-to-device (for accelerators) as
well as CPU-to-memory (for memory expansion and storage devices)
interconnects. Intel will produce Sapphire Rapids using its 10 nm Enhanced
SuperFin technology.
除了微结构创新外，新CPU还将配备DDR5内存控制器（加强的英特尔数据流加速器DSA）
，PCIe 5.0总线，数据传输速率为32 GT / s，并通过CXL 1.1协议进行了最佳化，以最佳
化CPU。到设备（用于加速器）以及CPU到内存（用于内存扩展和存储设备）的互连。
英特尔将使用其10nm增强型SuperFin技术生产SPR。
心得:
工程师有上厕所需求带新iphone导致照片外流
可以理解
CPU也照片露出...
以前:chiplets延迟过高
未来:真香
(情报文刷p币也是...)