来自国外老Intel人的分析
基于某些事实
2023量产7nm相当TSMC 5nm
GAAFET是更先进的制程技术
Intel最多让C52等四年就能重返农药(咦?
爱用三星的老黄
那精妙如达文西手术的刀法或将重出江湖
原文连结:
https://reurl.cc/OqNZDA
TSMC To Fall Behind Both Intel, Samsung By 2024
Summary
TSMC is currently seen as the most advanced semiconductor company, a position
it inherited from Intel due to latter’s 3-year 10nm delay.
However, a recent report indicates that TSMC will only move to
gate-all-around (GAA) transistors in 2025.
This will readily trail Samsung’s 2022 as well as Intel’s 2024 introduction
of GAAFETs.
This means TSMC could go from first to third within the next four years.
概要
台积电目前被视为最先进的半导体公司，由于英特尔3年的10nm延迟，它从英特尔那里继
承了这一地位。
然而，最近的一份报告表明，台积电将在2025年才采用GAAFET制程技术。
这将紧随三星在2022年以及英特尔在2024年推出GAAFET之后。
这意味着台积电在未来四年内可能会从第一掉到第三。
Overview
TSMC (TSM) is currently widely seen as the leader in semiconductor
technology. However, this is not something it achieved by doing anything
noteworthy: TSMC inherited this status from Intel (INTC) as the latter took
five years to launch its first 10nm product, whereas Moore’s Law calls for a
two-year cadence. TSMC did nothing but continue to adhere to said cadence.
总览
台积电（TSM）目前被广泛视为半导体技术的领导者。但是，这并不是通过做任何值得注
意的事情来实现的：台积电从英特尔（INTC）继承了这一地位，因为后者花了五年时间才
推出了其首款10nm产品，而摩尔定律则要求两年的节奏。台积电什么也没做，只是继续遵
守上述节奏。(译注:在讲龟兔赛跑, Intel没输, 只是在睡觉...)
Indeed, in an article early this year (and that admittedly has become
outdated since Intel announced its 7nm delay), I already noted that TSMC
itself was not particularly moving fast, also falling behind the Moore’s Law
curve: TSMC was transitioning from 5nm (N5) to 3nm (N3) on a
longer-than-usual 2.5-year cadence, while also increasing density by much
less than the 2.0x Moore’s Law calls for: for example, SRAM density will
only improve by a meager 1.2x. (So at the time, I noted that this gave Intel
an opportunity to catch up, but Intel subsequently delayed its 7nm, which
previously was intended to allow Intel to move on quickly from its plagued
10nm node.)
确实，在今年年初的一篇文章中（自英特尔宣布7nm延迟以来，这已经过时了），我已经
指出，台积电本身并没有特别快地发展，也落后于摩尔定律曲线：台积电正在从5nm（N5
）过渡）到3nm（N3）的速度比通常的2.5年更长，而密度的增加也远少于摩尔定律所要求
的2.0倍：例如，SRAM密度仅提高了1.2倍。（因此，当时我注意到这给了英特尔一个追赶
的机会，但英特尔随后推迟了其7纳米制程，这以前是为了使英特尔能够从受困的10nm
节点上迅速发展。）
Recently, the first report about 2nm (N2) has arrived. As expected, this will
mark TSMC’s transition from the FinFET transistor, first introduced by Intel
in 2012 before being adopted by TSMC in 2015, to the gate-all-around
transistor or GAAFET. Notably, TSMC is slated to move back to 2-year cadence,
which implies an early 2025 market introduction of N2, after a decade of
FinFET.
最近，有关2nm（N2）的第一份报告已经到来。正如预期的那样，这将标志着台积电从
FinFET晶体管过渡到gate-all-around FET或GAAFET.(FinFET晶体管由英特尔于2012年首次
引入，然后于2015年由台积电采用。)值得注意的是，台积电计划将回归两年制程，这意味
著在使用FinFET十年之后，N2将于2025年初进入市场。
The issue with this is that TSMC’s two remaining leading edge competitors,
Samsung and Intel, are both scheduled to move to the GAAFET ahead of TSMC.
This means that TSMC could go from first to third by 2024.
问题在于，台积电剩下的两个领先的竞争对手三星和英特尔都计划在台积电之前迁移到
GAAFET。这意味着台积电到2024年可能会从第一落到第三。
For investors, that means they should not assume TSMC is the last foundry
standing to pursue Moore’s Law, as competition is set to intensify.
对于投资者来说，这意味着他们不应该认为台积电是追求摩尔定律的最后一家半导体工厂
，因为竞争将加剧。
Terminology
I use GAAFET (gate-all-around) as the general term for a transistor whose
gate surrounds all four sides of the channel. A FinFET surrounds three sides,
and a planar one only one side.
术语
我将GAAFET（gate-all-around）用所有四面环绕闸极的晶体管的代称。FinFET围绕三个侧
面，而平面仅一个侧面。
Samsung mostly uses the term MCBFET (multi-channel bridge) or nanosheet.
三星通常使用术语MCBFET或nanosheet。
Samsung differentiates this from a nanowire, which as the name suggests is
more like a wire than sheet of paper, in terms of geometry.
三星将其与nanowire区分开来，顾名思义，nanowire就几何而言更像是线而不是纸。
A last name, mostly used by Intel, is nanoribbon. From the pictures from
Intel's research, this seems similar to a nanosheet, but perhaps it is a bit
in between both.
Inte主要使用nanoribbon。从英特尔研究的图片来看，这似乎与nanosheet相似，但可能介
于两者之间。
Lastly, node names: TSMC uses Nx, while Samsung and Intel continue to use xnm.
最后，节点名称：TSMC使用Nx，而Samsung和Intel继续使用xnm。
TSMC: N5, N3, N2
As widely known, TSMC has moved to N5 in the second half of 2020, at a
two-year cadence compared to N7. However, initial findings suggest that while
the cadence is on par with Moore’s Law, the shrink is not. In particular,
the Apple (AAPL) A14 only achieved a density of 134MT (133 million transistor
per mm2). This represent an increase of just 49% compared to 90MT on the A13.
台积电：N5，N3，N2
众所周知，台积电已于2020年下半年迁移到N5，与N7相比，以两年的节奏发展。但是，初
步发现表明，虽然节奏与摩尔定律相当，但收缩率却没有。特别是，Apple（AAPL）A14仅
实现了134MT的密度（每平方毫米1.33亿个晶体管）。与A13的90MT相比，这仅增长了49％
。
This compares to TSMC’s claim of a 1.8x shrink with N5, which would result
in a standardized density of 170MT. This lower shrink achieved by Apple can
be attributed for a large part due to the much lower SRAM (memory) shrink of
just 1.3x.
相比之下，台积电声称N5的收缩率是1.8倍，这将导致标准密度为170MT。苹果实现的这种
较低的收缩在很大程度上可以归因于SRAM（快取内存）的收缩率低得多，仅为1.3倍。
As mentioned in the introduction, TSMC’s N3 will follow on a 2.5-year
cadence in the first half of 2023, as TSMC’s last FinFET node. While TSMC
itself calls it a full-node shrink, no reasonable analysis could really
describe it as such. Logic density scaling decreases further to just 1.7x,
while SRAM will only see a 1.2x improvement. Analog will hardly shrink at all.
如导言所述，作为台积电的最后一个FinFET节点，台积电的N3将于2023年上半年遵循2.5
年的节奏。虽然台积电本身称其为全节点收缩，但没有任何合理的分析可以真正描述它。
逻辑密度缩放比例进一步降低至1.7倍，而SRAM仅提高1.2倍。模拟量几乎不会收缩。
Intel’s analysis half a decade ago showed that SRAM and analog comprise
40-50% of Apple’s chips, so a real-world density of no more than 50% should
be expected despite a 2.5-year cadence.
英特尔十年前的分析表明，SRAM和类比芯片占Apple芯片的40-50％，因此，尽管有2.5年
的节奏，但现实世界中的密度预计不会超过50％。
The newest information concerns N2. This node will move to GAAFET or MBCFET.
TSMC intends to start risk production in the second half of 2023. This
implies a two-year cadence compared to N3.
在最新的信息涉及N2。该节点将移至GAAFET或MBCFET。台积电计划在2023年下半年开始风
险生产。与N3相比，这意味着两年的节奏。
Given that risk production lags volume by approx. 12 months, and given that
volume production lags product introduction by ca. 6 months (for example, N5
risk production started in H1’19, followed by the iPhone 12 launch 18 months
later), this implies TSMC’s N2 gate-all-around will enter the market in the
first half of 2025.
鉴于这种风险，生产滞后量约。大约12个月，并且考虑到批量生产落后于产品推出的时间
。6个月（例如，N5风险生产于19年上半年开始，随后iPhone 12于18个月后推出），这意
味着台积电的N2 GAAFET将在2025年上半年进入市场。
Intel: 7nm, 5nm
Intel launched its 10nm in the second half 2020, and recently followed this
up with 10nm SuperFin, which Intel claimed delivers the same benefits as a
full-node jump would provide, in power and performance. (Obviously not in
density.)
英特尔：7nm，5nm
英特尔于2020年下半年推出了10nm技术，最近又推出了10nm SuperFin技术，英特尔声称
该技术在功耗和性能方面可提供与全节点跃迁相同的优势。（显然不是密度。）
Intel announced in July 2020 it would shift its 7nm ramp by 6 to 12 months,
which means volume availability is shifting from 2022 to 2023. While
specifications of 7nm aren’t known yet, Intel has previously indicated it
would be 2.0x or 2.4x shrink: at 200-240MT, it could be a fair bit denser
than TMSC N5. It will still be a FinFET.
英特尔在2020年7月宣布将其7nm的升级时间推迟6到12个月，这意味着批量供货时间将从
2022年转移到2023年。虽然尚不知道7nm的规格，但英特尔之前曾表示它将是2.0倍或2.4
倍。收缩：在200-240MT时，它可能比TMSC(原文错字) N5密度高一点。它将仍然是FinFET
。
(译注: TSMC 5nm为171.3MT)
In June, Intel’s CTO confirmed however that Intel would make the transition
to GAAFET “within the next five years”. The only process node that could
fulfill this promise is 5nm. Taken at face value, this means at worst Intel
will introduce GAAFET and 5nm in 2025, on par with TSMC. Intel has also said
5nm would be a 2x shrink.
然而，6月，英特尔首席技术官确认英特尔将在“未来五年内”过渡到GAAFET。可以满足
这一承诺的唯一工艺节点是5nm。从表面上看，这意味着最坏的情况是，英特尔将在2025
年推出GAAFET和5nm，与TSMC持平。英特尔也曾表示，5nm将密度增加2倍。
Q: Can you give us the timeline for the introduction of nanoribbon/nanowire
process technology into high volume production?
A: This is not a roadmap talk, so I'll be vague and say within in the next
five years.
问：您能否给我们提供将nanoribbon/nanowire工艺技术引入大批量生产的时间表？
答：这不是路线图讨论，所以我会含糊地说说在未来五年内。
However, Intel’s roadmap is more aggressive than 2025. Intel announced in
2019 (before the 7nm delay) that it intended to go back to a 2-year cadence.
A roadmap until 2029 also confirmed this. Given that 7nm was supposed to
enter the market in Q4’21, this implied 5nm would launch in Q4’23, which
Murthy confirmed:
但是，英特尔的路线图比2025年更具侵略性。英特尔在2019年（延迟7nm制程之前）宣
布，打算恢复为2年的节奏。直到2029年的路线图也证实了这一点。考虑到7nm应该在21年
第4季度进入市场，这意味着5nm将在23年第4季度推出，Murthy确认：
Comments on 5nm from Murthy:
- Excited about 5 and what they plan to deliver, well into development
- On track for 2023 (2-2.5 year cadence)
- Talked a lot about while they will be improving transistor performance,
power etc that Interconnect is also a big factor
Under the assumption that 5nm is now also shifting by 6 to 12 months (even
though a 7nm defect mode should have no impact whatsoever on 5nm development,
in principle), this still implies that 5nm will launch in 2024, up to a year
ahead of TSMC.
假设5nm现在也要转变6到12个月（即使从原理上讲7nm缺陷模式不会对5nm的发展产生任何
影响），这仍然意味着5nm将在2024年推出，比台积电提前一年。
Some may say that Intel may not fulfill its roadmap, but this article is
treating each vendor’s roadmap equally unless proven otherwise.
有人可能会说英特尔可能无法实现其路线图，但是除非另外证明，否则本文将平等对待每
个供应商的路线图。
Intel vs. TSMC
Intel’s 10nm process has a standardized (which means the comparison is
apples-to-apples) density of 100MT. While it obviously can’t be known how
large the A14 would be on Intel’s 10nm process (and its resulting real-world
density), in the past Apple’s SoC usually followed this standardized density
metric fairly well, which makes the seemingly low 134MT of the A14 especially
noteworthy.
英特尔对上台积电
英特尔的10nm制程的标准密度为100MT（这意味着同样标准之间的比较）。虽然显然无法知
道A14在Intel的10nm工艺上将有多大（及其最终的实际密度），但在过去，Apple的SoC通
常都很好地遵循了这种标准化的密度度量标准，这使得似乎低至134MT的A14特别值得注意
。(这是在说实际混和了SRAM和各种芯片的N5 A14 SOC密度有点低)
So assuming that the A14 would achieve 100MT on Intel’s 10nm process, this
suggests that in real-world density, TSMC may be just 1.35x ahead of Intel.
That is more akin to a half-node advantage compared to a full-node leap.
因此，假设A14在Intel的10nm工艺上将达到100MT，这表明在实际密度下，TSMC可能仅比
Intel高1.35倍。与全节点的飞跃相比，这更类似于半节点的优势。
(我自己不以为这样是apples to apples)
In other words, Intel may be not as much behind as many would assume.
Conversely, TSMC may also not be ahead as much would assume. Indeed, what
Intel may lack in density, it may make up for in other areas in transistor
(and packaging) technology, which it highlighted with its SuperFin technology
(and Lakefield 3D stacking).
换句话说，英特尔可能没有很多人想像的落后。反过来说，台积电也可能不如预期的那样
领先。确实，英特尔可能缺乏密度，但它可能会在晶体管（和封装）技术的其他领域得到
弥补，而英特尔在其SuperFin技术（以及Lakefield 3D堆栈）中强调了这一点。
Similarly, if N3 only improves density by another 50%, it may only achieve
closer to 200MT than the theoretical 300MT, which again might be closer to
Intel’s 7nm than 5nm.
同样，如果N3仅将密度提高50％，则只能实现比理论上的300MT更接近200MT的水平，后者
又可能比5nm更接近英特尔的7nm。
To validate this claim, more data about die sizes and transistors counts from
multiple chips should be required from both Intel and TSMC, but Intel stopped
releasing transistor counts around 2014: Intel argued that since its chips
had a vastly different composition in terms of logic cells, I/O and SRAM (see
image above), that any comparisons to Apple's transistor counts were
misleading. In other words, all of Intel's CPUs have a markedly lower
full-chip density than the standardized density.
为了证实这一说法，英特尔和台积电都需要更多有关多个芯片的芯片尺寸和晶体管数的数
据，但英特尔在2014年左右停止发布晶体管数：英特尔认为，由于其芯片在逻辑单元方面
存在很大差异，I / O和SRAM（请参见上图），与Apple晶体管数量的任何比较都具有误导
性。换句话说，所有英特尔CPU的全芯片密度均明显低于标准密度。
(这就是为什么我不认为是apples to apples, 至少不能拿理论去比实际混成的SOC)
Samsung
Samsung is currently ramping its 5nm process. Samsung has made some efforts
this year to assure press and investors that its 5nm process was not having
yield issues, contrary to various reports.
三星
三星目前正在加快其5nm制程。与各种报导相反，三星今年已做出一些努力向媒体和投
资者保证其5nm制程没有产量问题。
Samsung’s 5nm is not a new node, but a direct derivative of its 7nm
platform. As such, its density improvement will be even less than TSMC’s N5,
and should be not much higher than Intel’s 10nm.
三星的5nm并不是一个新节点，而是其7nm平台的直接衍生产品。这样，它的密度改进将甚
至不及台积电的N5，也不应高于英特尔的10nm。
Samsung’s 3nm node will mark its next big step, and as Samsung has announced
long ago, will mark its introduction of MCBFET, an industry-first. The node
seems to be delayed somewhat, as it now targeted for 2022 volume production
(compared to late 2021 previously). Samsung further claims a 0.65x or 0.55x
shrink, which should put it around the density of TSMC’s 5nm rather than 3nm.
三星的3nm节点将标志着其下一步发展，正如三星很久以前宣布的那样，它将标志着其业
界首创MCBFET的推出。该节点似乎有所延迟，因为它现在的目标是2022年的量产（之前是
2021年末）。三星进一步声称缩小了0.65倍或0.55倍，这应该使其接近TSMC 5nm而不是
3nm的密度。
Still, as discussed TSMC’s N3 will be more like half-node shrink, so what
Samsung may lack in density, it may make up in technology and time to market
– not unlike Intel.
不过，正如所讨论的台积电N那样3将更像是半节点收缩，因此三星可能密度不太增加
，它可能会在技术和上市时间上有所弥补-与英特尔不同
In that regard, Samsung’s early introduction of GAAFET will be similar to
Intel’s FinFET at 22nm, as the latter was comparable in density to TSMC’s
planar 28nm. While Samsung won’t hold a density advantage, it will still be
ahead of TSMC by up to three years, and ahead of Intel by up to two years in
introducing this technology in the market. In any case, Samsung already
announced in 2019 it is intending to invest over $100 billion this decade to
catch up to TSMC.
在这方面，三星早期推出的GAAFET与22nm的Intel FinFET相似，因为后者的密度可与台积
电的平面28nm相媲美。虽然三星将不会拥有密度优势，但在市场上推出这项技术的领先地
位仍然领先于TSMC三年，领先于Intel两年。无论如何，三星已经在2019年宣布它将计划
在这十年内投资超过1000亿美元以赶上台积电。
Takeaway
TSMC, currently seen as the market leader, may lose its process technology
leadership by 2024 or sooner.
结论
目前被视为市场领导者的台积电可能会在2024年或更早之前失去其工艺技术的领导地位。
The FinFET transistor, introduced in 2012 by Intel several years ahead of the
rest of the industry (as one example of how relatively quick things can
change), is running out of steam. As such, it has to be replaced by the
GAAFET. While this transition won’t be as drastic as the initial change to
FinFET was, it nevertheless is a major one. Just like the FinFET, it will
mark the start of a new era of process technology and chip design.
英特尔在2012年推出了FinFET晶体管，该晶体管在同行业中比其他行业领先了几年（这是
事物可以相对快速地变化的一个例子），但这种晶体管已经用尽了。因此，必须用GAAFET
代替它。虽然这种转变不会像FinFET最初的转变那样剧烈，但它是一个重大的转变。就像
FinFET一样，它将标志着制程技术和芯片设计新时代的开始。
This means that vendors who may have falling during the FinFET, may have an
opportunity to catch up. Indeed, current data suggests TSMC will be the last
vendor make this transition, up to one year behind Intel and three years
behind Samsung.
这意味着可能在FinFET期间跌落的供应商可能有机会追赶。确实，目前的数据表明，台积
电将是最后一次实现这一转变的厂商，比英特尔落后了一年，三星落后了三年。
Given the slowing of for example SRAM density scaling and the introduction of
3D logic stacking, and other unknows, the introduction of GAAFETs may perhaps
be seen as a (more) reliable indicator of process technology leadership going
forward, which I previously already argued is more than just transistor
density: Intel Vs. TSMC: Process Technology Leadership Is More Than
Transistor Density (NASDAQ:INTC).
考虑到SRAM密度缩放的放慢和3D逻辑堆栈的引入以及其他一些未知因素，GAAFET的引入可
能被视为工艺技术领先地位的（更可靠）指示，我之前已经指出过不仅仅是晶体管密度：
IntelVs。台积电（TSMC）：工艺技术的领导地位远胜于晶体管密度（纳斯达克：INTC）
。
(大哥没有输, 技术上)
In the past, Samsung has already served as the foundry for Apple, Nvidia
(NVDA) and Qualcomm (QCOM) among others. So Samsung's differentiated GAAFET
roadmap could have real foundry market share implications, while Intel
continues to recover from its 10nm and 7nm delays seeking to regain process
leadership.
过去，三星曾担任Apple，Nvidia（NVDA）和Qualcomm（QCOM）等公司的代工厂。因此，
三星差异化的GAAFET路线图可能会对晶圆代工市场产生实际影响，而英特尔继续从其10nm
和7nm延迟中恢复过来，以寻求重新夺回工艺领先地位。