[求救] 积电作业 HW3 verilog

楼主: TommyKSHS (汤米)   2011-12-13 22:52:09
我跑了 ncverilog +access+r tb_Comparator_51.v lib.v Comparator_51.v
这个指令后
出现了
The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
TOOL: ncsim 08.20-s024
HOSTNAME: cad32
OPERATING SYSTEM: SunOS 5.10 Generic_118833-24 sun4u
MESSAGE: sv_seghandler - SIGSEGV while handling SIGSEGV
System task: $fsdbDumpvars
file: ./tb_Comparator_51.v
line: 52
有哪位先进知道这该怎办…
原本以为逃离资结就不会有 segmentation fault 了
结果连 verilog 都会 segmentation fault 是怎样… QQQQ

Links booklink

Contact Us: admin [ a t ] ucptt.com