课程名称︰ 数位系统与实验
课程性质︰ 必修
课程教师︰ 欧阳明
开课学院：
开课系所︰ 资工系
考试日期（年月日）︰2014/04/23
考试时限（分钟）： 180 min
是否需发放奖励金：是
（如未明确表示，则不予发放）
试题 :
1.(12%) Convert the following Boolean expressions or K-map into Sum of
Products with the indicated number of literals. Recall that a literal
is either a variable or its negation.
(Hint: You may use K-map to speed up the computing)
(1) F (A, B, C, D) = Σ(2, 3, 10, 11, 12, 13, 14, 15)
(reduce to 4 literals)
(2) A'C'+ ABC + AC' (reduce to 3 literals)
(3) A'B(D' + C'D) + B(A + A'CD) (reduce to 1 literal)
(4) (B' + A)‧(B + C)
(5) A
┌─┬─┬─┬─┐
│ 0│ 0│ 0│ 0│
├─┼─┼─┼─┤
│ 1│ 0│ 0│ 1│
├─┼─┼─┼─┤D
│ 1│ 0│ 0│ 1│
C├─┼─┼─┼─┤
│ 1│ 1│ 1│ 1│
└─┴─┴─┴─┘
B (reduce to 4 literals)
(6)
A
┌─┬─┬─┬─┐
│ X│ 0│ 0│ 1│
├─┼─┼─┼─┤
│ 0│ X│ 0│ 1│
├─┼─┼─┼─┤D
│ 0│ 0│ X│ X│
C├─┼─┼─┼─┤
│ 1│ 0│ 0│ X│
└─┴─┴─┴─┘
B (reduce to 4 literals)
2.(10%) Consider the 5-bit binary equation "comparator" : The first 2-bit
is input A, the third bit is operator bit C where 0 means "add" while 1
means "subtract", and the last 2-bit is input B. Both A and B are
binary signed integer. If the equation occurs overflow (cannot be
represented by 2-bit binary signed integer), the ouput K will be 1,
otherwise, K will be 0.
For example:
11 0 10 = -1 + (-2) = -3 (overflow), output = 1
00 1 11 = 0– (-1) = 1 (safe), output = 0
(1) Draw the K-map for K
(2) Write the Boolen expressions for the output K
3.(3%) (1) Demonstrate that a 2-bit NOR gate is a universal logic element.
You can do this by showing how they can be used to make: NOR, AND,
OR, and XOR gates.
(6%) (2) Is an XOR gate a universal logic element? Why or why not?
(3%) (3) What about a 2-input NAND gate?
Note that each input of the NOR gate must be used, it cannot be left
unconnected.
4.(12%) You are a testing assistant in the bulb factory. The factory has just
produced 256 new bulbs numbered from 0 to 255 in binary number and
needs you to examine them. So you design a series of tests shown as
below. If the bulb is checked in some round, the entry of the bulb
should be set as 1, or 0 if unchecked. But this list is a waste of
paper, the boss ask you to simplify the list to Boolean function.
Please satisfy his requirement.
┌──┬─────────────┬─┬─┬──┬─┐
│ No.│Binary number [N7N6...N0] │R0│R1│....│Rn│
├──┼─────────────┼─┼─┼──┼─┤
│ 0 │ 00000000 │1 │ │ │ │
├──┼─────────────┼─┼─┼──┼─┤
│ 1 │ 00000001 │1 │ │ │ │
├──┼─────────────┼─┼─┼──┼─┤
│ 2 │ 00000010 │1 │ │ │ │
├──┼─────────────┼─┼─┼──┼─┤
│ 3 │ 00000011 │1 │ │ │ │
├──┼─────────────┼─┼─┼──┼─┤
│ . │ . │. │. │ . │. │
│ . │ . │. │. │ . │. │
├──┼─────────────┼─┼─┼──┼─┤
│254 │ 11111110 │0 │ │ │ │
├──┼─────────────┼─┼─┼──┼─┤
│255 │ 11111111 │0 │ │ │ │
└──┴─────────────┴─┴─┴──┴─┘
For instance, you have tested the first 4 bulbs (No.0 ~ No.3) bulbs
in Round 0, so you write down the Boolean function as
─ ─ ─ ─ ─ ─
R0 = N7‧N6‧N5‧N4‧N3‧N2
Please finish the rest (as simple as possible):
(1) R1 = Test the even numbers
(2) R2 = Test the multiples of 8
(3) R3 = Divide the bulbs into quarters. Test the 2nd and the 3rd
quarter
(4) R4 = Test all except for the last 32 bulbs
(5) R5 = Test all except for the multiple of 16
(6) R6 = Test No.129 and No.219 only
5. For a circuit with an inverter and an exclusive or gate, suppose that
the exclusive or gate has no time delay:
(4%) (1) What the output signal Y will be like with the input signal X?
(4%) (2) Why does Y have such relationship with X?
(4%) (3) What can the circuit do in real life?
http://i.imgur.com/mjyuxqK.png
6.(12%) The following figure shows how the hexadecimal 7-segment display
decoder works. DCBA is a 4-bit binary number input, then the decoder
will transfer the binary number into segment signal. Assume that 1 is
for segment "on" while 0 is segment "off".
http://i.imgur.com/0ZoJZRs.png
http://i.imgur.com/K2ULjYW.png
For instance, if DCBA represent the digit “0”, which means all the
segment except for "g" should be on. So the decoder will send (1, 1, 1,
1, 1, 1, 0) to the 7-segment display. Answer the following questions:
(1) If this decoder can only display decimal number (0 - 9), how many
bits are needed for the input ?
(2) If the output is unique, How many bits for the input of 7-segment
are valid at most ?
(3) Write the truth table for this hexadecimal 7-segment display system
(4) Draw the PLA implementation of this decoder in the following
template
http://i.imgur.com/LizjC27.png
7.(10%) Find a function to detect an error in the representation of a decimal
digit in BCD. In other words, write an equation with value 1 when the
input are any one of the six unused bit combinations in the BCD code
(10, 11, 12, 13, 14, 15), and value 0 otherwise. Please implement it
with only NAND gates and inverters.
8.(20%) Optional problem, you can choose either problem A or B below to answer:
Problem A:
A sequential circuit has two JK flip-flops with state outputs A, B and
two input X, Y (Note: inputs to flip-flop A are called JA, JB, while
inputs to B are called Jb, KB, circuit output is called Z). The circuit
is described by the following input equtions:
JA = XA + XY , KA = X'Y, and JB = XA, KB = Y, Z = YB where X' is the
compliment of X.
(10%) (1) draw the above circuit and derive the state tables,
(10%) (2) then draw the state diagram of this circuit.
Problem B: (Verilog HDL – Code Debugging)
Identify syntax errors and inappropriate code then correct them and
explain: 2 pts for each error.
┌───────────────────────────┐
│module 16x16-MAC (out, rst, op1, op2) │
│ │
│input clk, rst; │
│ │
│input [15:0] op1, op2; │
│ │
│output [39:0] out; │
│ │
│reg [31:0] product; │
│ │
│assign product = op1 * op2; │
│ │
│//40-bit accumulator after 16x16 multiplier │
│ │
│always @(posedge clk || negedge rst) │
│ │
│ if(rst) out= 0; │
│ │
│ else out = out + product; │
│ │
│endmodules │
│ │
└───────────────────────────┘