Trying to allow some instructions to take fewer cycles does not help, since th
e throughput is determined by clock cycle; the number of pipe stages per instr
uction affects latency, not throughput.
第一段话了解，意思应该是每个clock cycle会完成一个指令
让某些指令走少一些cycle对throughput没有帮助
分号后那一段觉得不通
Pipeline的stage数，切的数目好坏，有的可能让latency变更长
这样throughput不是也会变差吗？
谢谢！