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讲者是多伦多大学的教授，目前开了一家 verification/debugging 的 startup。
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Time: 10:00 ~ 11:30am, 04/08 (Thursday)
Place: BL 103
Robust QBF Encodings for Sequential Circuits with
Applications to Verification, Debug and Test
Andreas Veneris
University of Toronto
Department of Electrical and Computer Engineering
Department of Computer Science
ABSTRACT
Formal CAD tools operate on mathematical models describing the sequential
behavior of a VLSI design. With the growing size and state-space of modern
digital hardware designs, the conciseness of this mathematical model is of
paramount importance in extending the scalability of those tools, provided
that the compression does not come at the cost of reduced performance.
Quantified Boolean Formula satisfiability (QBF) is a powerful generalization
of Boolean satisfiability (SAT). It also belongs to the same complexity class
as many CAD problems dealing with sequential circuits, which makes it a
natural candidate for encoding such problems. This work proposes a succinct
QBF encoding for modeling sequential circuit behavior. The encoding is
parametrized and further compression is achieved using time-frame windowing.
Comprehensive hardware constructions are presented to illustrate the proposed
encodings. Three notable CAD problems, namely bounded model checking, design
debugging and sequential test pattern generation, are encoded as QBF
instances to demonstrate the robustness and practicality of the proposed
approach.
Unlike previous QBF-based encodings for verification problems, the presented
work provides a general-purpose QBF-based representation for a multitude of
CAD applications. It is designed to reduce memory requirements but also
achieve competitive run-times when compared to state-of-the-art SAT. Indeed,
extensive experiments on OpenCore circuits show memory reductions in the order
of 90% and demonstrate competitive run-times compared to state-of-the-art SAT
techniques. Furthermore, the number of solved instances is increased by 16%.
Admittedly, this work encourages further research in the use of QBF in CAD
for VLSI.
VITA
Andreas Veneris received a Diploma in Computer Engineering and Informatics
from the University of Patras in 1991, the M.S. degree in Computer Science
from the University of Southern California, Los Angeles in 1992 and the Ph.D.
degree in Computer Science from the University of Illinois at Urbana-
Champaign in 1998. In 1998-99 he was a visiting faculty at the University of
Illinois. Since 2004, he is an Associate Professor cross-appointed with the
Department of Electrical and Computer Engineering and the Department of
Computer Science at the University of Toronto. His research interests include
algorithms and CAD tools for debug, verification, synthesis and test of
digital systems and circuits. He is co-recipient of a best paper award in
ASP-DAC 2001, co-author of two books and he holds several patents. He is a
member of IEEE, ACM, AAAS, Technical Chamber of Greece, Professional
Engineers of Ontario and The Planetary Society. Since 2006, he is President/
CEO of Vennsa Technologies, the first company that commercializes automated
solutions to RTL debugging.