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IEEE SSCS Taipei Chapter Short Course
A System's Approach to Building Modern High-Speed Links
Prof. Vladimir Stojanovic
Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology
一、场次
<第一场> 国立交通大学光复校区工四馆国际会议厅
1月31日(星期三) 9:00~12:00，13:30~16:30
<第二场> 国立台湾大学电机二馆105视听教室
2月01日(星期四) 9:00~12:00，14:00~17:00
二、报名日期
即日起至01月30日止；一律上网报名
http://powereric.ee.ntu.edu.tw/~sscs/lectures/stojanovic/index.html
三、报名费用
(含讲义、午餐及点心，恕不退费)
IEEE Member Non-IEEE Member
业界 4000 4500
教师 1000 1500
学生 500 1000
四、缴费方式
(1) 请将支票或汇票挂号寄到‘10617台北市大安区罗斯福路四段一号
国立台湾大学电机二馆347室 李孋伦小姐收’。
(2) 支票或汇票抬头‘李孋伦’。
(3) 请在支票或汇票背面用铅笔注明‘单位’、‘姓名’及‘报名序号’。
(4) 请于01月30日前将支票或汇票寄达。
五、洽询办法
(1) 电话: (02)2363-5251 ext.367，李孋伦小姐。
(2) Email: necoppp@cc.ee.ntu.edu.tw
六、主办单位
国立台湾大学电子工程研究所
IEEE SSCS Taipei Chapter
七、课程大纲
Over the past decade, high-speed interfaces have increased the data
rates from 100's Mb/s in early 90's to tens of Gb/s today. Until
recently, these data rate improvements were mostly due to innovations
in building the fast multiplexing transmitters and receivers that
overcome the inherent speed limitation of the IC technology and also
due to increasingly better clock generation and recovery. However,
today's high-speed interfaces are limited by the bandwidth of the
communication channel, tight power constraints and noise sources that
differ from those in standard communication systems. The wire bandwidth
limitations make straight circuit solutions inefficient, and the power
and area constraints make standard digital communication approaches
infeasible. Efficient solutions require bridging the fields of digital
communications, optimization, statistical and dynamic system modeling,
with system architecture, mixed-signal and digital circuit design.
This short course covers the system and design issues relevant to
modern high-speed electrical signaling. We start by introducing the
basics of channel properties, modeling, measurements, and communications
techniques. The system design issues such as planning and budgeting are
also presented. We then present the basics of link hardware components
like clock generation (PLL, DLL) and recovery, multiplexed drivers,
modulators and equalizers. System-driven circuit design of main
components is covered in detail. Using the insight from these link
models and circuits, we can drive the efficient implementation of
custom signal processing that is needed to cover given performance space.
Several examples of state-of-the-art links will be presented throughout
the tutorial, from high-performance DRAM parallel links to serial-links
for high-end router and blade server backplanes.
八、主讲人简介
Prof. Stojanovic received his M.S. and Ph.D. in Electrical Engineering
from Stanford University in 2000 and 2005, respectively. He is currently
an Assistant Professor in the Department of Electrical Engineering and
Computer Science and a member of both Research Laboratory of Electronics
(RLE) and the Microsystems Technology Laboratories (MTL) at the MIT,
where he directs the Integrated Systems Group. Prof. Stojanovic currently
holds a 2006 Doherty Professorship at MIT. From 2001 through 2004, he
was also a principal engineer in Rambus, Inc., Los Altos, CA, where he
made key contributions to Rambus' serial-link technology and patent
portfolio. During 1997-1998, he was a visiting scholar with the Advanced
Computer Systems Engineering Laboratory, Department of Electrical and
Computer Engineering, University of California, Davis.
Please refer to the short course webpage for more information.
http://powereric.ee.ntu.edu.tw/~sscs/lectures/stojanovic/index.html